Capacitor device and wiring pattern

ABSTRACT

A capacitor device is provided which includes a plurality of electric double-layer capacitors connected in series, and a balance resistor portion where five resistors having an equivalent resistance are connected in parallel. In this capacitor device, the balance resistor portion is connected to each electric double-layer capacitor, so that the electric double-layer capacitors connected in series can be charged uniformly.

TECHNICAL FIELD

The present invention is the art of a capacitor device in which electricdouble-layer capacitors are used.

BACKGROUND ART

In recent years, a capacitor device where an electric double-layercapacitor is used has been promised as a mechanical-power source for anelectric automobile or the like. In such an electric double-layercapacitor, as its electrode, an active carbon is used which has a largespecific surface area and is electrochemically inactive. This electrodeis immersed in an electrolyte, and an electric charge is generated onthe interface between the electrode and the electrolyte. Then, thiselectric charge is stored in the electric double layer so that it can beused in the capacitor.

An electric double-layer capacitor has a low withstand voltage (i.e., arated voltage) of two to three volts. Hence, a capacitor device isgenerally configured by several electric double-layer capacitors.Besides, in an electric double-layer capacitor, the capacitance,internal resistance or the like of each element is known to vary widely.Therefore, if a capacitor device is formed by several electricdouble-layer capacitors, some of such devices can be fully charged soonwhile some may take a long time to charge. Hence, there is adisadvantage in that each electric double-layer capacitor cannot becharged in balance.

As the art of resolving this disadvantage, a “balance circuit system” isknown. FIG. 6 is a circuit diagram, showing a circuit which embodies a“balance circuit system”. The circuit shown in FIG. 6 is made up of n(which is a positive number) electric double-layer capacitors C101 toC10 n which are connected in series, and n balance resistors R101 to R10n. The balance resistors R101 to R10 n each have an equivalentresistance and are connected in parallel to the electric double-layercapacitors C101 to C10 n. Thereby, a bias voltage applied to eachelectric double-layer capacitor C101 to C10 n is equal, thus helpingcharge each electric double-layer capacitor in a well-balanced state.

Furthermore, in another circuit (refer to Japanese Utility ModelLaid-Open No. 5-23527 specification) which realizes a “balance circuitsystem”, a balance resistor is electrically separated from an electricdouble-layer capacitor at a non-charge time. When the voltage betweenboth ends of this capacitor becomes a predetermined value or above, thecapacitor is connected in parallel to the balance resistor. Thisprevents an electric discharge at a non-charge time, thus helping storeelectrical energy for a long time.

Moreover, still another circuit (refer to Japanese Patent Laid-Open No.6-343225 specification) which embodies a “balance circuit system”includes a comparison circuit which compares the voltage between bothends of an electric double-layer capacitor and a charging referencevoltage, and a by-pass circuit which receives an output from thecomparison circuit and by-passes a charging current for the electricdouble-layer capacitor. The height of the charging reference voltage ischanged suitably for various uses, so that the bias voltage of theelectric double-layer capacitor can be regulated.

DISCLOSURE OF THE INVENTION

However, any of the inventions described in the circuit shown in FIG. 6,Japanese Utility Model Laid-Open No. 5-23527 specification and JapanesePatent Laid-Open No. 6-343225 specification has the followingdisadvantages. A single balance resistor is connected in parallel to anelectric double-layer capacitor. Therefore, the dispersion of theresistance of such a balance resistor makes it impossible to chargeelectric double-layer capacitors uniformly.

Furthermore, if a balance resistor is broken and opened, the biasvoltage given to an electric double-layer capacitor rises largely. Thus,the bias voltage applied to each electric double-layer capacitor isthrown out of balance. This presents a disadvantage in that eachelectric double-layer capacitor cannot be charged in balance. Moreover,another disadvantage also arises in that the bias voltage may exceed therated voltage of an electric double-layer capacitor, thereby destroyingthe electric double-layer capacitor.

It is an object of the present invention to provide a capacitor devicewhich is capable of charging electric double-layer capacitors in balanceand preventing the electric double-layer capacitors from being damaged.

A capacitor device according to the present invention, characterized byincluding: a plurality of electric double-layer capacitors which areconnected in series; and a balance resistor portion in which m (which isan integer of two or above) resistors having an equivalent resistanceare connected in parallel, the balance resistor portion being connectedin parallel to each electric double-layer capacitor.

According to this configuration, to each of several electricdouble-layer capacitors connected in series, a balance resistor portionin which m (which is an integer of two or above) resistors having anequivalent resistance are connected in parallel is connected inparallel. Therefore, the resistance of the balance resistor portion canbe restrained from varying widely. This helps charge each electricdouble-layer capacitor uniformly. Further, even if a part of theresistors which form the balance resistor portion is broken to turn intoan open state, then because there are the other resistors connected inparallel, the bias voltage given to the electric double-layer capacitoris kept from being higher. This helps prevent the electric double-layercapacitor from being destroyed. Consequently, the capacitor devicebecomes more reliable, thus preventing the whole of an apparatus towhich the capacitor device is connected from malfunctioning. Stillfurther, even if any resistor is damaged, the bias voltage applied toeach electric double-layer capacitor is kept in balance. This allows thecapacitor device to function normally.

In addition, preferably, the resistance of the balance resistor portionshould be equal to, or less than, one-fourth the resistance of eachresistor which forms the balance resistor portion.

According to this configuration, the resistance of the balance resistorportion is equal to, or less than, one-fourth the resistance of eachresistor which makes up the balance resistor portion. In other words,the number of the resistors which make up the balance resistor portionis four or above. Therefore, even if any one of the resistors which makeup the balance resistor portion is broken and opened, the resistance ofthe balance resistor portion can be restrained from going up beyond 25percent. This contributes toward keeping the rise in the bias voltage at25 percent or under. Hence, if the value of the bias voltage is set at25 percent or less of the rated voltage of the electric double-layercapacitor, the value of the bias voltage is more unlikely to exceed therated voltage, though any resistors are damaged and opened. This helpslengthen the life span of the electric double-layer capacitor.

Furthermore, it is preferable that the resistance of the balanceresistor portion be equal to, or more than, one-sixth, and theresistance of each resistor which forms the balance resistor portion.

According to this configuration, the resistance of the balance resistorportion is equal to, or more than, one-sixth the resistance of theindividual resistor. In other words, the number of the resistors of thebalance resistor portion is six or below. Therefore, a restraint can beplaced on the rise in the bias voltage which may be caused by a brokenresistor. At the same time, the power loss which is caused by theincrease in the number of resistors can be reduced. Thereby, theelectric charge stored in the electric double-layer capacitor can berestrained from being discharged.

Moreover, preferably, the resistance of the balance resistor portionshould be equal to, or more than, one-sixth the resistance of eachresistor and should be equal to, or less than, one-fourth thisresistance.

According to this configuration, the lifetime of the electricdouble-layer capacitor can be extremely lengthened. Simultaneously, theelectric charge stored in the electric double-layer capacitor can berestrained from being discharged.

In addition, it is preferable that the resistance of the balanceresistor portion be 100Ω or above and 500Ω or below.

According to this configuration, at the time of a charge and adischarge, a loss can be reduced in the electric double-layer capacitor.

Furthermore, preferably, the number of electric double-layer capacitorsconnected in series should be set so that a bias voltage given to eachelectric double-layer capacitor is lower than the rated voltage of theelectric double-layer capacitor.

According to this configuration, the bias voltage applied to eachelectric double-layer capacitor is lower than the rated voltage. Thishelps prevent the electric double-layer capacitor from being destroyed.

Moreover, it is preferable that one or a plurality of electricdouble-layer capacitors be further connected in parallel to the balanceresistor portion.

According to this configuration, one or several electric double-layercapacitors are further connected to the balance resistor portion. Inother words, the electric double-layer capacitors are connected in amatrix form, such that the electric double-layer capacitors connected inparallel are connected in series. This makes it possible to offer acapacitor device which has a superior durability and a greatcapacitance.

A wiring pattern according to the present invention in which a pluralityof electric double-layer capacitors are connected in parallel,characterized in that: the wiring pattern includes three or more wiringpatterns disposed at a predetermined interval; a plurality of electricdouble-layer capacitors are connected in parallel between adjacentwiring patterns; and between two adjacent electric double-layercapacitors which are connected between the wiring patterns, a pluralityof resistors having an equivalent resistance are connected in parallelto the electric double-layer capacitors.

According to this configuration, three or more wiring patterns aredisposed so that their longitudinal directions are parallel. Betweenadjacent wiring patterns, several electric double-layer capacitors areconnected in parallel. Between two adjacent electric double-layercapacitors, several resistors are connected in parallel with theelectric double-layer capacitors. Therefore, the full length of thewiring pattern can be shortened. This helps reduce the resistance ofwiring, thus enhancing the charge and discharge efficiency of theelectric double-layer capacitor.

Besides, between several wiring patterns disposed in parallel, severalresistors and several electric double-layer capacitors are electricallyconnected. Therefore, even when resistors are broken, the bias voltagegiven to the electric double-layer capacitor can be kept from beinghigher, because there are the other resistors connected in parallel.This helps prevent the electric double-layer capacitor from beingdamaged.

In addition, preferably, the resistors should be connected from onewiring surface of the wiring pattern, and the electric double-layercapacitors should be connected from the other wiring surface of thewiring pattern.

According to this configuration, the electric double-layer capacitorsare connected to one wiring surface of the wiring pattern, and theresistors are connected to the other wiring surface of the wiringpattern. Therefore, the overall length of the wiring pattern becomesshorter than in the case where both elements of the electricdouble-layer capacitors and the resistors are connected only from theside of one wiring surface of the wiring pattern. This helps lessen theresistance of wiring, thus enhancing the charging and dischargingefficiency of the electric double-layer capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a capacitor device according to a firstembodiment of the present invention.

FIG. 2 is a circuit diagram of a capacitor device in which the number ofresistors which make up a balance resistor portion is three.

FIG. 3 is a circuit diagram of a capacitor device in which the number ofresistors which make up a balance resistor portion is seven, comparedwith the capacitor device of FIG. 2.

FIG. 4 is a circuit diagram of a capacitor device according to a secondembodiment of the present invention.

FIG. 5 is an illustration of the structure of the capacitor device shownin FIG. 4, showing the case where the number of cell groups CL1 to CLnis seven.

FIG. 6 is a circuit diagram of a capacitor device according to a priorart.

BEST MODE FOR IMPLEMENTING THE INVENTION

Hereinafter, embodiments of the present invention will be described withreference to the attached drawings.

First Embodiment

FIG. 1 is a circuit diagram of a capacitor device according to a firstembodiment of the present invention. As shown in FIG. 1, this capacitordevice includes n (which is an integer of two or above) electricdouble-layer capacitors C1 to Cn, and n balance resistor portions R1 toRn. Hereinafter, the “electric double-layer capacitor” is referred tosimply as the “capacitor”. The capacitors C1 to Cn are connected inseries. The balance resistor portions R1 to Rn are connected in parallelto the capacitors C1 to Cn, respectively.

The balance resistor portions R1 to Rn each have the same configuration,and thus, only the balance resistor portion R1 will be described. Thebalance resistor portion R1 is provided with five resistors R11 to R15connected in parallel. The resistors R11 to R15 each have an equivalentresistance. As the resistors R11 to R15, a chip type or a lead-wire typecan be used. However, the present invention is not limited especially tothis.

The capacitors C1 to Cn each have the same configuration, and thus, onlythe capacitor C1 will be described. The capacitor C1 is formed in thefollowing way. A drawn-out lead wire is attached to an aluminum foilwhich is etched at a thickness of 20 to 50 μm. This foil's upper surfaceis coated with a paste which is made of a mixed powder obtained bymixing an active-carbon powder with a bonding agent and a conductiveagent which are desirable. Thereby, a conductive layer is formed. Onthis conductive layer, active-carbon layer polarization electrodes areformed which include an active carbon as the principal component. Thus,a pair of electric double-layer electrodes is formed. These electricdouble-layer electrodes are placed to face each other via a separator.Then, they are wound around so that a capacitor element is formed.Sequentially, this capacitor element is impregnated with an electrolytesolution. Then, it is inserted in an aluminum case and its opening partis sealed.

The withstand voltage of the electric double-layer capacitor isdetermined according to what kind of electrolyte solution it is.Besides, this withstand voltage determines the rated voltage of theelectric double-layer capacitor. Ordinarily, the rated voltage of oneelectric double-layer capacitor is within a range of 2 to 3 V.

Between the capacitors C1 to Cn shown in FIG. 1, a DC voltage V isapplied to charge each capacitor. To each capacitor C1 to Cn, thebalance resistor portions R1 to Rn which have an equivalent resistanceare connected in parallel, respectively. Hence, the bias voltage (V/n)is given which is obtained by dividing the DC voltage V by the number ofcapacitors.

Herein, as the capacitor Ci which has a rated voltage of 2.6V and acapacitance of 100 F, six capacitors are connected in series. Theresistance of resistors Ri1 to Ri5 is 100Ω. To both ends of thecapacitors C1 to C6, a DC voltage of 12 V is applied so that thecapacitors C1 to C6 can be charged. In this case, because the resistanceof resistors R11 to R11 is 100Ω, the resistance of the balance resistorportion R1 is 20Ω which is obtained by dividing 100 by 5.

In this case, the bias voltage of each capacitor C1 to C6 is 2.0 V whichis obtained by dividing 12 V by 6. This value is lower than the ratedvoltage 2.6 V of the capacitors C1 to C6. Thus, the capacitors C1 to C6can be prevented from being damaged. Therefore, preferably, the number nof capacitors which are connected in series should be n>V/VT, if the DCvoltage given to both ends of the capacitors connected in series is Vand the rated voltage of each capacitor is VT.

Next, this capacitor device will be compared with a conventionalcapacitor device, in terms of a change in the bias voltage when abalance resistor is damaged. In a conventional capacitor deviceincluding a single balance resistor, if the resistor is broken andopened, the bias voltage given to a capacitor rises largely. This isbecause no resistors connected in parallel are provided, different fromthe capacitor device according to this embodiment. Therefore, capacitorsconnected in series cannot be charged in balance. Besides, the biasvoltage may exceed the rated voltage of the capacitor, thus destroyingthe capacitor.

On the other hand, in the capacitor device according to this embodiment,even if the resistor R11 of the balance resistor portion R1 is brokenand turns into an open state, the four resistors R12 to R15 stillremain. Therefore, after the resistor R11 is broken, the resistance ofthe balance resistor portion R1 is kept down to 25Ω/20Ω=1.25 times asgreat as its resistance before the resistor R11 is broken. Hence, thebias voltage of the capacitor C1 becomes 2.0V×1.25=2.5V, withoutexceeding the rated voltage 2.6 V of the capacitor C1. This helpsprevent the capacitor C1 from being damaged.

Next, description will be given about, preferably, how many resistorsshould make up the balance resistor portion Ri. FIG. 2 is a circuitdiagram of a capacitor device in which the number of resistors whichmake up the balance resistor portion R1 is three. The resistance ofresistors Ri1 to Ri3 is r. The rated voltage of capacitors C1 to C6 is2.6 V. To both ends of the capacitors C1 to C6, a voltage of 12 V isapplied.

In the capacitor device shown in FIG. 2, let's assume that a resistorR11 is damaged. In this case, a balance resistor portion R1 turns into acircuit in which two resistors R12, R13 are connected in parallel.Thereby, its resistance becomes r/2. On the other hand, before theresistor R11 is damaged, the resistance of the balance resistor portionR1 is r/3. Therefore, after the resistor R11 is damaged, the resistanceof the balance resistor portion R1 becomes (r/2)/(r/3)=1.5 times asgreat as that before it is damaged, 50 percent up. This also causes thebias voltage to rise by 50 percent. Consequently, the bias-voltage valueof the capacitor C1 becomes 2.0×1.5=3.0V, and thus, exceeds the ratedvoltage 2.6 V of the capacitor C1.

FIG. 3 is a circuit diagram of a capacitor device in which the number ofresistors which make up a balance resistor portion R1 is seven, comparedwith the capacitor device of FIG. 2. In the capacitor device shown inFIG. 3, if a resistor R11 is broken, the resistance of a balanceresistor portion R1 turns into r/6. Hence, it becomes (r/6)/(r/7)=7/6times as great as that before it is broken, and thus, the increase inthe bias voltage is less than that of the capacitor device shown in FIG.2. From the point of view of restraining a broken resistor from going upthe bias voltage, it is preferable that the number of resistors whichmake up the balance resistor portion Ri be increased.

However, such an increase in the number of resistors makes their powerloss heavier. As a result, an electric charge may be dischargedimmediately after the charge has been given. Hence, preferably, thenumber of resistors which make up the balance resistor portion Ri shouldbe four to six. It is more desirable that it be five. In other words, itis preferable that the resistance of the balance resistor portion Ri beequal to, or more than, one-sixth the resistance of each resistor whichmakes up the balance resistor portion Ri and be equal to, or less than,one-fourth this resistance. It should be one-fifth, more desirably.

As described so far, in the capacitor device according to the firstembodiment, the balance resistor portions R1 to Rn are each formed bythe plurality of resistors Ri1 to Ri5 connected in parallel. Therefore,the resistance of each balance resistor portion R1 to Rn can be keptfrom dispersing, thus helping charge the capacitors C1 to Cn uniformly.

In addition, the balance resistor portion R1 is formed by the pluralityof resistors connected in parallel. Therefore, even if any resistors aredamaged and opened, then because there are the remaining resistorsconnected in parallel, the bias voltage can be restrained from beinghigher. This helps not only charge each capacitor C1 to Cn in balance,but also prevent the capacitors from being destroyed.

Incidentally, in view of a reduction in the loss at the time of a chargeand a discharge in the capacitors C1 to Cn, preferably, the resistanceof the balance resistor portion should be within a range of 10 to 500Ω.

Second Embodiment

FIG. 4 is a circuit diagram of a capacitor device according to a secondembodiment of the present invention. In the capacitor device accordingto the second embodiment, capacitors are connected in parallel, ascontrasted with the capacitor device according to the first embodiment.Specifically, the capacitor device shown in FIG. 4 includes n cellgroups CL1 to CLn connected in series, and n balance resistor portionsR1 to Rn connected in parallel to each cell group CL1 to CLn. To thei-th (i=1, 2, 3, . . . n) cell group CLi, four capacitors Ci1 to Ci4 areconnected in parallel. The balance resistor portions R1 to Rn has thesame configuration as those of the capacitor device according to thefirst embodiment shown in FIG. 1. Thus, their description is omitted.

In this way, even if the capacitors are connected in parallel so thatthe capacitor device's capacitance increases, the resistance of eachbalance resistor portion R1 to Rn can be restrained from dispersing.This is because the balance resistor portions R1 to Rn are connected inparallel to the cell groups CL1 to CLn. Consequently, the capacitors Ci1to Ci4 can be uniformly charged.

Furthermore, even if any of resistors Ri1 to Ri5 which make up thebalance resistor portion Ri is damaged and opened, then because theremaining resistors connected in parallel are provided, the bias voltageto the cell group CLi can be restrained from being higher. This helpsgive the bias voltage in balance to each cell group CL1 to CLn, thuspreventing the capacitors C11 to Cn5 from being damaged.

Moreover, four electric double-layer capacitors are connected inparallel, so that the capacitance can be heightened. Hence, thiscapacitor device can be used, for example, as each control power sourceor auxiliary power source for an electric automobile or the like whichrequires a large capacitance and a great quantity of current.Incidentally, in FIG. 4, the number of capacitors which make up the cellgroup CLi is four. However, it is not limited to this, and thus, two,three, five or more may also be provided.

Next, the structure of the capacitor device will be described. FIG. 5 isan illustration of the structure of the capacitor device shown in FIG.4, showing the case where the number of the cell groups CL1 to CLn isseven. As shown in FIG. 5, this capacitor device includes a circuitboard 10 on which eight wiring patterns 1 to 8 are printed, twenty-eightcapacitors C11 to C74 which are disposed in a matrix form of four linesand seven rows, and thirty-five resistors R11 to R75.

The Next, the wiring patterns 1 to 8 are formed by a conductor made ofcopper, silver or the like. They have a long and narrow shape and areformed at fixed intervals on the circuit board 10 so that theirlongitudinal directions are parallel. Herein, the distance between eachwiring pattern 1 to 8 is approximately equal to the pitch at which thecapacitors C11 to C74 are disposed.

In each wiring pattern 1 and 8, four convex portions 11 to 14 are formedat regular intervals along the longitudinal directions. Besides, in eachwiring pattern 2 to 7, four convex portions 11 to 14 are formed atregular intervals along one side in the longitudinal directions. Alongthe other side in the longitudinal directions, four convex portions 11to 14 are formed at regular intervals. Herein, the interval of eachconvex portion 11 to 14 is substantially equal to the disposition pitchof each capacitor C11 to C74. In each convex portion 11 to 14, a throughhole is formed into which the lead wire of each capacitor is inserted. Aconductor is formed on the inner wall of the through hole.

Between the convex portions 11 and 12, a T-shaped terminal 20 forconnecting five resistors is formed so as to protrude in the directionsperpendicular to the longitudinal directions of the wiring patterns 1 to8. In the wiring patterns 1 to 8, the convex portions 11 to 14 and theterminals 20 are formed so as to face each other.

Between the terminal 20 of the wiring pattern 1 and 12 and the terminal20 of the wiring pattern 2, five resistors R11 to R15 are connected. Inthe same way, between the other adjacent wiring patterns, five resistorsare also connected via the terminal 20. Thereby, the resistors R11 toR15 are connected in parallel. Similarly, the other resistors are alsoconnected in parallel.

Between the wiring patterns 1 and 2, the capacitors C11 to C14 areconnected from the opposite surface (or back surface) to the surface ofthe circuit board 10 onto which the resistors are connected. Between thewiring patterns 2 and 3, the capacitors C21 to C24 are connected; . . .; and between the wiring patterns 7 and 8, the capacitors C71 to C74 areconnected. Specifically, in the capacitor Cij (herein, i is an integerof one to seven, and i is an integer of one to four), one lead wire isinserted into the through hole of the convex portion 11 of the j-thwiring pattern j. Then, they are soldered together. The other lead wireis inserted into the through hole of the convex portion 11 of the wiringpattern j+1. Then, they are soldered up.

Thereby, the capacitors C11 to C14 are connected in parallel. The othercapacitors are connected in parallel as well.

As described above, the wiring patterns 1 to 8 are disposed in parallelso that their longitudinal directions are parallel. Then, severalcapacitors are connected in parallel between adjacent wiring patterns.Between two capacitors connected in parallel, the terminal 20 is formed.Then, five resistors are connected to this terminal 20. Between adjacentwiring patterns, four capacitors are connected from the back surface.Therefore, the full length of a wiring pattern can be shortened. Thishelps lower the wiring resistance, enhance the charge efficiency of thecapacitors C11 to C74, and make the circuit board 10 smaller.

Incidentally, in FIG. 5, the terminal 20 is formed between the convexportions 11 and 12. However, its formation is not limited to this, andthus, it may also be formed between other convex portions. In addition,the wiring patterns 1 to 8 are printed on the circuit board 10, buttheir configuration is not limited to this. A flat-plate member formedby a conductive member may also be used.

INDUSTRIAL APPLICABILITY

According to the present invention, a capacitor device can be providedwhich is capable of charging each electric double-layer capacitor inbalance and preventing the electric double-layer capacitors from beingdamaged.

1. A capacitor device, comprising: a plurality of electric double-layercapacitors connected in series; and a plurality of balance resistorportions each comprising m resistors connected in parallel with eachother and having equivalent resistance to each other, m being an integergreater than or equal to two; the plural balance resistor portions beingconnected in parallel to the plural electric double-layer capacitors,respectively.
 2. The capacitor device according to claim 1, wherein theresistance of at least one of the balance resistor portions is equal to,or less than, one-fourth the resistance of each resistor of said atleast one of the balance resistor portions.
 3. The capacitor deviceaccording to claim 1, wherein the resistance of at least one of thebalance resistor portions is equal to, or more than, one-sixth theresistance of each resistor of said at least one of the balance resistorportions.
 4. The capacitor device according to claim 1, wherein theresistance of at least one of the balance resistor portions is equal to,or more than, one-sixth the resistance of each resistor of said at leastone of the balance resistor portions and is equal to, or less than,one-fourth the resistance of each resistor of the at least one of thebalance resistor portions.
 5. The capacitor device according to claim 1,wherein the resistance of at least one of the balance resistor portionsis greater than or equal to 100Ω or above and less than or equal to500Ω.
 6. The capacitor device according to claim 1, wherein the numberof electric double-layer capacitors connected in series is set so that abias voltage given to each electric double-layer capacitor is lower thanthe rated voltage of the electric double-layer capacitor.
 7. Thecapacitor device according to claim 1, wherein one or a plurality ofelectric double-layer capacitors are further connected in parallel to atleast one of the balance resistor portions.
 8. A wiring patterncomprising: three or more wiring patterns disposed at a predeterminedinterval; a plurality of electric double-layer capacitors connected inparallel between adjacent wiring patterns; and between two adjacentelectric double-layer capacitors which are connected between the wiringpatterns, a plurality of resistors, having an equivalent resistance,connected in parallel to the electric double-layer capacitors.
 9. Thewiring pattern according to claim 8, wherein the resistors are connectedfrom one wiring surface of the wiring pattern, and the electricdouble-layer capacitors are connected from another wiring surface of thewiring pattern.